Expert Hardware / RTL Engineer

June 2, 2026
Application ends: August 31, 2026

Job Description

REQUIREMENTS

  • 5+ years of professional or research RTL experience in SystemVerilog or Verilog
  • Hands-on depth in RTL design, testbench/UVM verification, FPGA or ASIC work, and EDA toolchains (Vivado, Quartus, Synopsys, Cadence)
  • Comfort working in Linux/Docker-based repo environments and reading automated/CI checks — or the ability to ramp on these fast
  • Ability to articulate not just what code does but why it’s correct or idiomatic, clearly in writing

RESPONSIBILITIES

  • Apply your RTL expertise to evaluate technical tasks against real-world professional standards
  • Review intricate code-level situations and provide precise, structured written assessments
  • Work inside containerized repositories (Docker), running and interpreting programmatic and CI-style checks to judge whether an engineering environment is sound
  • Provide clear written rationales explaining your expert judgments
  • Complete well-defined, time-bounded tasks with explicit evaluation criteria

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